A VLSI architecture for real-time image convolution with large symmetric kernels

The authors propose VLSI architectures for real-time convolution of an image by any large kernel with symmetries. Consideration is limited to horizontal, vertical, and central symmetries in order to reduce the hardware requirements. Based on these architectures, a chip is proposed which would implement a real-time convolution of 512*512 images with kernels up to 11*11 and allow online processing of video format images.<>