A parallel architecture graphics processor

A parallel architecture for realizing a graphics system for real-time display of computer-generated images is proposed. The graphics architecture is configured with an arbitrary number of identical channels. The screen display space is partitioned into n/sup 2/ zones. The implementation algorithms are distributed in three stages of n processors connected by n*n switches. The first stage rasterizes the objects. The second stage generates the depth values for the intermediate pixels when it receives two matching tags (i.e. two pixels with the same y coordinate). The x coordinates are then used as tags to communicate the depth values to the third stage. Since the depth values are passed, finding the minimum removes the hidden surfaces. Each channel generates its own version of the screen, and a combination unit combines these versions to produce the final image.<
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