Design and automatic generation of a CMOS NOR-NOR testable programmable logic array (CTPLA)

A CMOS NOR-NOR testable PLA (CTPLA) which has a universal test set is discussed. Berkeley VLSI tools were used to implement and verify the design. The PLA contains an extra row and a column, along with a shift register and two cascades of exclusive-OR (EXOR) gates, to make it testable. The layout of the CTPLA was implemented such that the inherent regularity of the PLA can be maintained without undue compromise. A procedure which automatically generates the layout according to a given personalization was written. The test set detects all single stuck-at faults as well as crosspoint faults.<
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