An efficient software-controlled PLL for low-frequency applications

The concept of a software-controlled phase-locked loop (SCPLL) is presented. It is shown that SCPLLs can offer several advantages over pure hardware implementations. An example design of an SCPLL for a power converter controller is presented, and the experimental results are reported. This SCPLL can efficiently substitute for the conventional hardware PLL used for timing and clock frequency multiplication in the control circuit of a power converter.<
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