Designing IEEE 1149.1 compatible boundary-scan logic into an ASIC using Texas Instrument's Scope architecture

A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it.<
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