A pipelined ASIC for color matrixing and convolution

A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2- mu m CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications.<
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