A note on designing a comprehensive scanning electron microscopy test structure (for VLSI)

The authors have developed a family of computer generated test structures for scanning electron microscopy (SEM) sectioning. These test structures were designed to provide maximum topography and design rule process data with minimum sample preparation. The test structures were designed to be large enough to allow cleaving through the structures. The individual layout geometries were repeated in a staggered fashion across the structure to maximize the probability that a cleave will not require multiple passes of polishing to locate the position of interest. All the SEM structures were placed together so that a single sample makes all included physical parameters observable.<
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