A new method and test structure for easy determination of femto-farad on-chip capacitances in a MOS process

A new method and test structure for the easy measurement of on-chip capacitances are described. With relatively simple equipment an accuracy that allows measurements in the femto-farad range can be obtained. Test structures have been realized on a test chip in a 1.2- mu m CMOS process in a gate array environment. The accuracy of the method was demonstrated with a comparative measurement of a chip-external 10-pF capacitance with a conventional method. The measurements of on-chip capacitances showed good conformity to simulations. It was shown that the method is well suited for measurements with a digital verification tester and a wafer prober with minimum overhead.<
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