An analog front end for full-duplex digital transceivers working on twisted pairs

An analog front-end chip fabricated in a 4- mu m CMOS process has been described. The chip, together with a digital signal processor, implements a full-duplex transceiver for twisted pairs. A fully differential architecture has been used in all the analog signal-processing blocks to get high dynamic range and common-mode noise rejection. The front-end output is a 12-b word generated by a 6- mu s A/D (analog-to-digital) converter with autocalibration, with a linearity better than 1 LSB.<
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