Multilevel simulation tool for designing fault-tolerant VLSI array processors

The authors present the design details of an integrated CAD tool for efficient realization of parallel processors for high throughput in real-time digital signal processing (DSP) applications. The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level. Core of this tool is a functional-structural simulator which is embedded into an environment supporting array processor design. One of the most important features of this CAD tool is that advanced fault-tolerance techniques can be incorporated in an early design phase not only to achieve high reliability and long life time but also to enhance production yields.<
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