A scan-based BIST technique using pair-wise compare of identical components

Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a reduction in test time of about 20 times for a module with 50 ASICs. The extra board area required was less than 2% for all boards of the module.<
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