A performance-aimed cell compactor with automatic jogs

To develop an efficient cell compactor for practical use, the authors take the one-dimensional compaction approach, but with a mixed symbolic and shape data model. A new algorithm of automatic jog generation is employed to create jogs, not only on critical paths but also on some noncritical paths. An optimum wire length minimization algorithm is used to tighten wires and polygon edges. These algorithms help reduce both the cell size and the parasitic, and hence produce high-quality layouts. The compactor has been used at IBM in the production of several standard cell libraries and macrocells,.<
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