Planarization of dielectric layers for multilevel metallization

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO/sub 2/ films formed over the abrupt topography of fine-line (2.0- mu m pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO/sub 2/ must be maintained at approximately 0.4 (3800 and 9100 AA/min, respectively) with an Ar/CF/sub 4//O/sub 2/ high pressure plasma generated in a low radio-frequency etching system.<
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