An accurate timing model for gate-level simulation of MOS circuits

The authors describe an accurate delay model for gate-level simulation of digital MOS circuits. Results from electrical-level simulation are given to present evidence that input-dependent, state-dependent delays as well as charge-storage effects must be considered in addition to intrinsic and load-dependent delays. A comprehensive simulation algorithm with limited overhead is discussed. It takes into account all these factors and it is fully compatible with event-driven selective-trace simulation.<
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