Parametric yield enhancement of analogue integrated circuits: a new approach

Two algorithms for the parametric yield enhancement of analog ICs have been developed. Those parameters which are under the designer's control are geometric in nature and are collectively represented by a point in geometric space (G-space) whose axes are typically device widths. The aim of the yield enhancement algorithm is to move the point in G-space representing the design to a new location with which is associated a maximum-and hopefully 100%-manufacturing yield. Parameter adjustments can be automated but demand efficient algorithms. Both algorithms are based on a proven statistical design centering technique for discrete component circuits, modified to account for the particular characteristics of IC design. Designed for use within an automated analog design environment, both algorithms are robust and feature cost-saving techniques. However, it appears that the relative efficiency of these algorithms is influenced by the size of the design problem.<
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