BiCMOS defect-modelling and fault analysis

Common defects are modeled for BiCMOS logic gates. Only 54% of the defect set simulated in the BiCMOS test circuits manifested themselves in terms of a failure in the logical behavior of the gate. This would suggest that test vector sets designed on the premise of testing for logical failures would be less appropriate for BiCMOS than for CMOS gates where 69% of the defect set caused logical failures. However, 95% of the defects simulated in the BiCMOS test circuits caused failures that could be characterized as either a failure in the logical behavior of the gate or as a delay fault. These results indicate that, by applying logical-fault testing in combination with delay-fault testing, fault coverage should be increased to more acceptable levels.<
>