A manufacturable 0.4 mu m process for high-performance LSI circuits

To increase the performance of GaAs LSI digital circuits, a new 0.4 mu m fabrication process is developed which demonstrates excellent yields for E/D logic circuits of up to 5000 gates. The refractory self-aligned gate process uses stepper-compatible 1 mu m lithography. An n/sup +//n'/buried-p structure results in excellent threshold voltage uniformity for a 0.4 mu m gate length, with sigma V/sub T/ as low as 8 mV over 3" wafers. Die-sort yields for a 16*16-bit multiplier chip are typically better than 55%, and as high as 88%. For a 20*20-bit multiplier chip, yields have been as high as 61%. Multiplication times of 3.6 ns for the 16*16-bit and 4.5 ns (46 ps/gate) for the 20*20-bit multiplier have been measured, representing the fastest room-temperature operation yet reported for such multipliers. LSI fabrication process, yield evaluation, and circuit performance are described.<
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