Linear algorithms for optimizing the layout of dynamic CMOS cells

In many CMOS design styles the basic building blocks are complex (static or dynamic) CMOS gates with up to a few dozen transistors. The layout optimization for such gates takes the shape of graph optimization problems. Two such graph problems, corresponding to different layout styles for basic cells composed of dynamic CMOS gates, are considered. Both problems are solved in linear time; the number of gates in the cell is considered.<>