Applying WSI methods to emitter de-interleaving

Examines the application of WSI (wafer scale integration) to a computationally intensive problem-emitter de-interleaving. In the context of an electronic battlefield, both friendly and hostile RF emitters must be identified and sorted. This formidable task is expected to require a computer power of 7 Gb/s. A reconfigurable WSI technique quilted logic array is used to map this problem onto a wafer. In this approach, an array of several hundred processors is used to solve the emitter de-interleaving problem. The form of the panels may be optimized for the particular application with processors, memory, or floating point functional units. Flexible interconnections allows varying numbers of processor panels to be applied to the signal processing functions. It is shown how the emitter de-interleaving problem can be solved using one 6-in wafer.<
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