Simplified max-log-MAP decoder structure

Area efficient turbo decoder structures are needed in 3G receivers. Typically, max-log-MAP decoders are used as component decoders. In this paper, it is shown that all the computations of the max-log-MAP algorithm can be carried out with slightly modified add compare select (ACS) units. All the required computations of the max-log-MAP algorithm are analyzed and they are mapped to the proposed ACS units (ACSU). A set of four ACSUs is multiplexed to carry out the computations. With the presented method, the structure of the max-log-MAP decoder is simplified and the computing resources are shared economically