High speed synchronization module implemented in altera stratix II FPGA

This paper presents programmable FPGA-based divider of high frequency reference signal dedicated to generate various frequencies for synchronization of particle accelerator subsystems. The digital circuit was synthesized using pure VHDL description thus can be implemented not only in target Altera Stratix II high-speed FPGA chip but other FPGAs as well. The implemented circuit operates up to the FPGA frequency limit of 500 MHz. The generated frequency signals can be time shifted by programmable multiplicity of the clock period (2ps) without introducing additional phase skew to the output signals