The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

A novel circuits and design methodology of the massively parallel processor based on the matrix architecture is introduced. Unique circuit design of the parallel fine-grained processing elements enhances the performance of MAC (multiply-accumulate) operation up to 30.0GOPS/W. Hierarchical memory architecture with super wide internal bus and distributed power management contribute to the enhancement of the processing efficiency and the robustness of the macro. The proposed circuit design methodology proposed in this paper is especially effective for realizing high-performance, robust processing macro employed in SOCs