A Register File with 8.4GHz Throughput for Efficient Instruction Scheduling in a Pentium~ 4 Processor

This paper describes a unique register file (RF) for ping-pong operation in 65nm CMOS process. The merged ping-pong reduces array width by 50%, doubles the frequency of access, and allows for same phase read and write. Implementation as a dependency matrix allows for all read wordlines to be asserted at once. A bypass scheme merged with the bitline contributes to a 27% leakage saving