Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

We have developed a novel junction profile engineering using laser spike annealing (LSA) with co-implant and applied it to sub-30-nm strained CMOS devices. A 55% reduction in source-drain extension (SDE) resistance achieves a 15% improvement in the saturation on-current (I
_on
) at a 28-nm gate length for PMOS. A reduction in the source-dram parasitic resistance enables an over 50% improvement in the linear on-current (I
_dlin
) by capping layer stress on the 29-nm gate length, which is about a 10% increase in the I
_dlin
improvement ratio compared to that of the control device, and a 28% of I
_on
enhancement gave us I
_on
= 460 μA/μm for I
_off
= 100 nA/μm at V
_d
= -1.0 V. For NMOS, low resistance SDE can be obtained without inducing the deterioration of the V
_th
-rolloff thanks to the halo profile modulation, and 6% of I
_on
enhancement was achieved at a 29-nm gate length, and I
_on
= 925 μA/μm for I
_off
= 100 nA/μm at V
_d
= 1.0 V was obtained