Novel FUSI Strained Engineering for 45-nm Node CMOS Performance Enhancement

FUSI metal gate with strained engineering is extensively investigated and reported for the first time. Enveloped FUSI (fully silicided) phase transfer and volume change induced stress exhibits 10% NMOS I
_ON
enhancement. Further, the second CESL (contact etch stop layer) induced stress raised another 8% NMOS I
_ON
gain. Although the first CESL on poly-gate top removed by FUSI CMP leads to 10% PMOS I
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degradation, it can be recovered or further improved by a dual CESL process