A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Cell for Ultimate Multi-Bit Operation

We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front side (FS) and ~1.1V for back side (BS) at V
_DS
=1.2V was obtained. The V
_TH
shifts of ~1.5V for both program/erase (P/E) were observed with the P/E conditions, V
_D
/V
_FG
=3/5V, 3/-4V for FS and VD/VBG=3.2/7V, 3.2/-5V for BS, respectively, with the duration of 1 ms. The V
_TH
windows of ~0.9V for FS and ~1.1V for BS were achieved even after 10
⁴
P/E cycles