Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 mum, the inner-sidewall-oxide fringing capacitance (C
_FIS
), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V
_G
=0.3 V and V
_D
=1 V, is the second largest contributor to the gate-source capacitance (C
_GS
). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 mum, C
_FIS
cannot be overlooked for modeling gate-source/drain capacitance (C
_GS
/C
_GD
)