A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35 /spl mu/m CMOS

This paper describes a 10-bit analog-to-digital converter (ADC) for digital video broadcasting-handheld (DVB-H) systems. The ADC is based on a 2.5-2.5-2.5-4 bits-per-stage pipeline architecture and occupies an area of 1.3 mm
²
in a 0.35 mum CMOS process. At the target sampling rate of 20.48 MS/s, measured results show that the converter consumes 19.5 mW from a 1.5 V power supply and achieves 56 dB SNR and 60 dB SFDR. Effective resolution bandwidth is 100 MHz and energy consumption per conversion is 0.19 pJ