A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

This paper presents a low-complexity, high-speed VLSI decoder architecture and its FPGA implementation for Euclidian geometry (EG) based quasi-cyclic (QC) low-density parity-check (LDPC) codes. In the design, various optimizations are employed to increase the clock speed. More parallelism is enabled for the partially parallel decoding architecture through the introduction of small hardware overhead. An efficient non-uniform quantization scheme is proposed to reduce the size of soft message memories without sacrificing the decoding performance. Synthesis results show that the proposed decoder for a (8176, 7156) EG-LDPC code can achieve a maximum (information) decoding throughput over 170 Mbps on Xilinx Virtex II FPGA when performing 15 iterations.