Network-on-chip link analysis under power and performance constraints

This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links between adjacent routers and links between a router and an attached processing element (PE). Analytical models for global router-to-router links and semi-global router-to-PE links are studied. Power and performance optimizations are obtained for each of these two classes of interconnections.