Scalable high-throughput architecture for H.264/AVC variable block size motion estimation

Variable block size motion estimation (VBSME) is a key part of the new H.264/AVC video coding standard. This has increased the demand for high performance VBSME architectures. This paper proposes a VLSI architecture for high throughput VBSME. The VBS calculation is done by combining the results of sub-block calculations to form the results for larger blocks. High motion vector throughput is achieved in two proposed implementations: one performing operations on a 1/spl times/4 set of pixels per cycle, and the second performing operations on a 1/spl times/16 set of pixels per cycle. Using these approaches, the architecture is able to produce motion vector results at a higher throughput than current VBSME designs, while providing a high level of scalability through adjusting the length of the processing element array.