Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology

This paper reports a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique, for designing high-speed low-power SOC applications using 90nm MTCMOS technology. Based on this optimization technique, using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less power consumption as compared to the all low-threshold one