A CMOS image sensor for low light applications

We describe and analyze a novel CMOS pixel for high speed, low light imaging applications. The pixel achieves lower dark current and noise and increased gain in comparison with conventional three-transistor, one-photodiode active pixel sensors without sacrificing speed and scalability to large arrays. It accomplishes this by biasing the photodiode of each pixel near zero volts and by separating the photodiode from the floating diffusion integration node. An image sensor with a 256 /spl times/ 256 array of these pixels was designed for a commercially available 0.18 /spl mu/m CMOS technology. The pixel size is 5/spl mu/.m /spl times/ 5/spl mu/m with a fill factor of 31%. The chip area is 3000 /spl mu/m /spl times/ 3000/spl mu/m. 1.8 V and 3.3 V power supplies are used for logic and sensor array, respectively. Differential output and chip level correlated-double sampling are used to suppress fixed pattern noise. Transmission gates with dummy transistors are incorporated into the readout chain to reduce both clock feedthrough and charge injection.