Low power readout control circuit for high resolution CMOS image sensor

In this paper, we present a low power, shift-register-based, readout control circuit for high resolution CMOS image sensors. In this circuit, a clock tree with the proposed autonomous clock gating technique is build for the clock supply system. The dynamic power is lowered by decreasing the switch activities and load capacitances. Additionally, from our analysis and simulations, the dynamic power dissipation is demonstrated to increase in proportion to the logarithm of the size of an imager. In high resolution applications, the size of imager is very large. By using this proposed circuit, the dynamic power dissipation of a large imager increases slightly. Besides, in order to reduce the static power dissipation, the leakage current is decreased by using the technique of stack effect.