Design of a 1.8V 6bits Low Power F/I CMOS A/D Converter with a Novel Folder-Reduction Technique

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FOM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm
²
in 0.18um CMOS technology.