Design Techniques for VHF Filtering in Digital CMOS Technologies

In this paper we report a design strategy for VHF filtering in standard digital CMOS processes. The design approach is based on fully-balanced pseudo-differential continuous-time transconductors for applications in low-voltage systems over the VHF range and implemented with MOS-C accumulation capacitors. A 3rd-order G
_m
-C low-pass Butterworth filter has been implemented, using a 0.35 mum standard CMOS process, with a cut-off frequency programmability over the 40-200 MHz range, which confirm the feasibility of the proposed strategy in applications such as data storage systems and IF strips. The filter consumes less than 3.8 mW per pole at 41 MHz from a 2V supply. The measured dynamic range was better than 53 dB at THD of 1%. The active chip area is 0.02 mm
²
per pole