Design of a 125/spl mu/W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18/spl mu/m CMOS (Tsu-Ming Liu, 2006). The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108/spl mu/W and 125/spl mu/W respectively at 1V supply voltage.