System Level Methodology Evaluation of Reconfigurable Computing Architectures

Wireless communication standards evolve and change quickly and demands for new features, services and advanced functionality arise rapidly. To survive to this dynamic environment, equipment manufacturers move towards solutions that offer a good balance between implementation efficiency and flexibility. Reconfigurable computing systems have attracted a lot of attention because of their promise to achieve significant speedup on a general class of applications. In this paper, we proposed a system-level evaluation methodology of reconfigurable computing architectures. The evaluation approach enables us to study the system-level impact of the architectural design features on the computational performance. As a case study, we implemented a DVB-T receiver, and quantitatively investigated various design features of the reconfigurable element. The results validate our evaluation methodology and prove that reconfigurable processing architectures have the potential to yield significant speedups