Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs

Fault-injection experiments on Virtex-IItrade FPGAs quantify failure and degradation modes in I/O channels incorporating triple module redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated (LVCMOS at 3.3V and 1.8V) shows more configuration bits have a measurable detrimental performance effect when in error