Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has
$sim$
21% lower gate capacitance and lower
$I_ off$
by two orders of magnitude than a conventional saddle device under nearly the same
$I_ on$
. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time
$(CV/I)$
by
$sim$
30% than the conventional recess channel device while keeping nearly the same
$I_ off$
.