An All-Digital Clock Recovery Architecture for the BRAN Hiperaccess Uplink Receiver

In this work, an all-digital synchronization recovery circuit is proposed for the uplink scheme of the ETSI BRAN Hiperaccess receiver. In particular a fast, open-loop algorithm, which exploits the TDMA burst preamble made of 16 or 32 cazac symbols, is tested by means of a link-level simulator operating at twice the symbol rate. At the receiver we suppose to use a fixed local oscillator and the symbol timing recovery is performed by means of digital interpolation. The fractional delay parameter for a fourth and sixth order Farrow interpolator is computed by means of a second order polynomial representation of the maximum likelihood function. After the recovery of the symbol timing, the phase offset is adjusted by simply taking the argument of the log-likelihood function. Performances of the proposed architecture are evaluated by measuring the symbol error rate and the synchronization error variances on AWGN channel.