Polarity-dependent device degradation in SONOS transistors due to gate conduction under nonvolatile memory operations

In order to explain polarity-dependent device degradation observed in polysilicon-oxide-nitride-oxide-silicon (SONOS) transistors, a physics-based model is proposed. Comparing the trends in polarity-dependent electrical characteristics between two different gate dielectric structures of stacked oxide- nitride-oxide (ONO) and oxide alone (SiO/sub 2/), it was demonstrated that the bimodal behavior observed in SONOS transistors is due to the stacked gate dielectric structure and that the device degradation is caused not by electrons but by holes. The proposed model is based on two models of the anode hole injection with maximum available hole energy E/sub max/ and the hydrogen-released interface trap generation. It is shown that the device degradation /spl Delta//sup */ in the stacked-ONO gate structure can be expressed by the total fluence of the hole Q/sub Ah/ injected from the anode side as /spl Delta//sup *//spl ap/Q/sub Ah//sup 0.25/. Utilizing a threshold voltage shift /spl Delta/V/sub th/ method, it was found that the gate conduction in SONOS transistors is governed by a specific tunneling process, which depends on the voltage drop V/sub OX/ across the tunnel oxide. It is also shown that the gate conduction mechanism through the ONO stacks makes a smooth transition from one tunneling process to another depending on the relationship between the V/sub OX/ and the tunneling barrier height of /spl Phi//sub B/.