On Generating Multipliers for a Cellular Fast Fourier Transform Processor

One possible hardware implementation for the fast Fourier transform (FFT) of 2m samples is to have 2m-1 cells, each of which performs two of the necessary computations during each of the m passes through the processor. But in each of these m passes, each of the 2
^m-1
cells may require a different multiplier coefficient for its computations. The two most obvious solutions are costly. The multipliers could be stored in a central memory and sent to each cell when needed; however, it takes time to transmit them and uses many pins, or interconnections between cells. Alternatively, the multipliers could be stored in a ROM in each cell. This makes each cell bigger, and the cells are no longer identical copies of one another. We consider a third possibility in this note. In each pass the multipliers are generated from the values of the multipliers used in the previous pass. This technique requires no increase in the number of pins per cell and little increase in the time required to perform the Fourier transformation.