Design and Optimization of a Versatile 700 V SPIC Process Using a Fully Implanted Triple-well Technology

A SPIC (smart power IC) process with a wide range of devices up to 700 V has been designed and optimized. An important feature is that all the devices have been realized by using a fully implanted triple-well technology in a P-type single crystal without epitaxial layer or buried layer. The results of this process are the low fabrication cost, simple process and small chip area. In addition to high voltage lateral DMOS (HV-LDMOS) transistor with the breakdown voltage (BV) 700 V as well as JFET device and low voltage CMOS (LV-CMOS) transistors have been fabricated using this process, a NPN type bipolar transistor is also realized and optimized by a additional implantation and drive-in. The major features of this process for SPIC fabrication have been clearly demonstrated