Modeling and Analysis of Metal Interconnect Resistance of Power MOSFETs with Ultra Low On-Resistance

The issue of metal interconnect resistance becomes increasingly critical as the power MOSFET technology continues to advance. This paper introduces a three-dimensional finite element analysis (FEA) approach to model the influence of source metal on the performance of power MOSFETs with ultra low on-resistance. Various source metal interconnection designs for two commercial discrete packages, the D
²
PAK and DirectFET, are studied extensively using the newly developed FEA model. It is found that the number and location of wirebonds or solder pads as well as the interconnect layout all have considerable impact on the total on-resistance of a power MOSFET. Furthermore, the metal interconnect resistance imposes another limit on the lowest R
_DS(on)
that can be practically achieved on power MOSFETs even in light of the ever-decreasing silicon-contributed specific on-resistance