Continuous digital calibration of pipeline A/D converters

This paper describes a novel continuous calibration technique for pipeline analog-to-digital converters (ADCs). The new scheme utilizes an existing digital calibration algorithm and extends it to work in real time. The goal is to digitally calibrate the pipeline ADCs in the background without interrupting the normal operation of the converter. The concept behind the digital calibration algorithm is described and simulated using a 1-bit/stage pipeline architecture. Dominant static error mechanisms present in pipeline architectures are identified and discussed. These errors are successfully corrected by the implemented digital calibration algorithm. The calibration scheme is transparent to the overall system performance and is demonstrated using a 14-bit ADC with a 1-bit/stage architecture and 16 identical stages. The first seven stages in the pipeline are calibrated. Continuous calibration is realized using a hardware description language and two extra stages located at the end of the pipeline. The extra stages are only used during the calibration process. Verilog implementations of a stage-and-error-correction logic, as well as a finite state machine to control the calibration process, are presented. The real-time digital calibration technique is verified and successfully demonstrated using the Verilog-XL simulator.