Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes

Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semi-empirical analytical model to compute, at logic level, the impact of power supply voltage variations (/spl Delta/V/sub DD/) and/or of temperature variations (/spl Delta/T) on speed response of a digital module is proposed. The model allows low-cost fault simulation. Moreover, it is shown that delay variation can be emulated either by a /spl Delta/V/sub DDi/ or a /spl Delta/Tj variation. The on-chip availability of multiple V/sub DD/ values in products with DVS (dynamic voltage scaling) opens opportunities for novel BIST techniques. A new DVS-based BIST approach is proposed and its ability to detect and diagnose resistive open defects is ascertained.