Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs

We present a number of low-cost concurrent error detection (CED) schemes for finite state machines (FSMs) implemented using embedded memory blocks available in FPGAs. The experimental results show that for many of the examined benchmark circuits, some of the proposed schemes provide for a reasonable level of error detection at a very low circuitry overhead, not exceeding 10%. The proposed set of CED schemes offers the designer an opportunity to trade-off error detection efficiency with implementation cost