Highly Reliable Interface of Self-aligned CuSiN process with Low-k Sic barrier dielectric (k3.5) for 65nm node and beyond

A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) has been developed for 65nm node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure. In addition, 39times via electro-migration (EM) improvement and 1.5times better TZDB were obtained in comparison to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TEM-EELS. According to these analyses, the mechanism for performance enhancement is proposed