Fabrication of compliant, copper-based chip-to-substrate connections

A fabrication process for compliant, copper chip-to-substrate interconnections is described in this paper. Copper interconnect structures were produced through a copper electroplating step filling cavities inside photo-patterned hollow polymer molds. These polymer structures were fabricated on both the chip and the substrate. Copper pillar interconnects are useful as chip-to-substrate power distribution I/O and have been successfully fabricated and assembled. Finite element modeling by ANSYS was used to simulate the mechanics of the copper pillars connection from chip-to-board at elevated temperature conditions. The shear stress distribution was used to analyze the weak points along the pillar. The maximum allowed shear stress was then use to determine the required pillar dimensions (e.g. height and aspect ratio).